| Body na spoluautora | Body za publikaci pro MU | Odkaz ISVaV | | 0,00 | 0,00 | On Decidability of LTL+Past Model Checking for Process Rewrite Systems
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| 5,98 | 17,94 | On Decidability of LTL Model Checking for Process Rewrite Systems
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| 12,70 | 38,11 | Reachability is decidable for weakly extended process rewrite systems
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| 14,45 | 72,24 | VHDL Design Verification Tools
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| 0,00 | 0,00 | Weakly Extended Process Rewrite Systems
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| 4,11 | 12,32 | Reachability of Hennessy - Milner properties for weakly extended PRS
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| 4,82 | 14,45 | Reachability of Hennessy - Milner properties for weakly extended PRS
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| 0,00 | 0,00 | Refining Undecidability Border of Weak Bisimilarity.
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| 0,00 | 0,00 | Formal Verification of the CRC Algorithm Properties
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| 0,00 | 0,00 | Formal Verification of the CRC Algorithm Properties
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| 4,82 | 14,45 | Formal Verification of a FIFO Component in Design of Network Monitoring Hardware
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| 4,82 | 14,45 | On Decidability of LTL Model Checking for Process Rewrite Systems
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| 10,06 | 30,19 | On Decidability of LTL Model Checking for Process Rewrite Systems
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| 0,00 | 0,00 | On Decidability of LTL Model Checking for Weakly Extended Process Rewrite Systems
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| 0,56 | 1,68 | Packet Filtering for FPGA-Based Routing Accelerator
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| 6,71 | 20,14 | Petri Nets Are Less Expressive Than State-Extended PA
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| 24,08 | 72,24 | Sequence Chart Studio 0.1: Basic Verification Algorithms
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| 0,00 | 0,00 | Almost Linear Büchi Automata
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| 0,00 | 0,00 | On Decidability of LTL+Past Model Checking for Process Rewrite Systems
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| 2,89 | 14,45 | Verifying VHDL Designs with Multiple Clocks in SMV
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| 0,00 | 0,00 | Refining Undecidability Border of Weak Bisimilarity.
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| 10,06 | 30,19 | Refining Undecidability Border of Weak Bisimilarity
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| 0,00 | 0,00 | Routing and Level 2 Addressing in a Hardware Accelerator for Network Applications
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| 0,00 | 0,00 | Routing, L2 Addressing, and Packet Filtering in a Hardware Engine
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(c) Michal Bulant, 2011